1. Field of the Invention
Example embodiments of the present invention generally relate to semiconductor memory devices and methods of delaying a data sampling signal.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional input/output sense amplifier, which may be used in a memory device.
Generally in a semiconductor memory device, a memory array is arranged in columns and rows. To read data stored in the memory array, a row address is input to select an entire row. Then a column address selects one bit out of the selected row. In response to a column selection signal (CSL), the selected data are transferred to data input/output lines (DIO). The data transferred to the data input/output lines (DIO) are sampled in response to a predetermined data sampling signal (FRT) by an input/output sense amplifier (IO S/A) 10. The sampled data, i.e., sensed data, are output through output lines (DO). The data sampling signal FRT, may be one of various control signals of input/output sense amplifier (IO S/A) 10 that allows the input/output sense amplifier to latch the sensed data.
FIG. 2 is a timing diagram illustrating delay characteristics of input data of the conventional memory device when there is a difference in distance between a plurality of memory blocks and a sense amplifier. FIG. 3 is a timing diagram illustrating delay characteristics of input data of the conventional memory device operating at high speed when there is a difference in distance between a plurality of memory blocks and a sense amplifier.
In general, as the density of a semiconductor memory device increases, a length of the data input/output line (DIO) used for data transfer also increases. Accordingly, time required to transfer data through the data input/output lines (DIO) may differ depending on the length of the DIO. In other words, if a memory block (A) is spatially farther away from an input/output sense amplifier (IO S/A) than a memory block (B), data (DATA_LONG) read from the memory block (A) is received by the input/output sense amplifier (IO S/A) relatively later than when data (DATA_SHORT) read from the memory block (B) is received by the input/output sense amplifier (IO S/A). Thus, the time required to transfer data from the memory block (A) to the input/output sense amplifier (IO S/A) and the time required to transfer data from the memory block (B) to the input/output sense amplifier (IO S/A) may be different. In addition, the time required to transfer data from the same memory block (A or B) to the input/output sense amplifier (IO S/A) may vary depending on the location of data addresses. Also, the data input/output lines (DIO) may have an influence on the time required to transfer data to the input/output sense amplifier (IO S/A).
Referring to FIG. 2, data (DATA_SHORT) from the memory block (B) is received by the input/output sense amplifier (IO S/A) relatively faster than data (DATA_LONG) read from the memory block (A). Even if DATA_SHORT and DATA_LONG are transferred through a data input/output lines (DIO) connected to the same column selection signal (CSL), the arrival time for each data at an input/output sense amplifier (IO S/A) varies depending on the row address of the memory cell data.
When the column selection signal (CSL) is enabled, the data sampling signal (FRT) is enabled after data from the corresponding memory block arrives at the input/output sense amplifier (IO S/A).
Generally, the data sampling signal (FRT) starts data sampling in synchronization with the last arrived data at the input/output sense amplifier (IO S/A), and terminates the data sampling in synchronization with the first arrived data at the input/output sense amplifier (IO S/A). Thus, as shown in FIG. 2, the sampling signal (FRT) has a sampling period WINDOW corresponding to an overlap between effective periods of the DATA_SHORT and the DATA_LONG.
However, the sampling period WINDOW grows shorter as the difference in the time interval of the memory blocks' (A and B) respective arrival at the input/output sense amplifier (IO S/A) becomes longer. As shown in FIG. 3, in some cases, there is a risk that the sampling period WINDOW of the data sampling signal (FRT) may not exist for a high-speed semiconductor memory device.